1. Field of the Invention
The invention relates to systems for interfacing logic level control signals within an electrical load, and more particularly to a bi-directional control system for motor loads.
2. Description of the Prior Art
Systems for di-directional control of electrical loads, and in particular inductive loads, in response to logic level pulse commands, have taken several configurations in the prior art. The general requirements for such systems are good efficiency, small size and weight, and in particular freedom from current surges during change of the direction of load energization and from latch-up conditions which result either in directional ambiguity or in component failure due to excessive heat dissipation. One previous approach employed a complementary pair of transistor drivers in common emitter configuration. This approach has the disadvantage of requiring dual power supplies of opposed polarity and, when interfaced with logic level control signals, additional buffering and level shifting circuitry. Further, should control signals be applied to both inputs simultaneously, thereby energizing both output drivers, there could result the series interconnection of the power supplies of opposing polarities with resulting short-circuit catastrophic failure. Further, even in the absence of simultaneous application of the dual logic inputs, should a second input signal be applied immediately after the removal of the first input signal, a large current surge could result. This is attributed to the time for a saturated transistor switch, as commonly used, to turn off. Such period can be appreciably greater than the period for turning on. Thus, for a short interval of time, both directional drivers would be activated. This again results in the direct coupling of the power supplies of opposing polarity which effects the aforesaid short-circuit condition. In order to minimize this condition, an improved prior art circuit incorporated "dead-time" generation circuitry into the control system. Dead-time is herein defined as the delay between the time of turning off a first output device and reducing the consequent flow of current in a first selected direction to zero value, to the time of turning on a second output device and inducing the corresponding flow of current in the opposing direction. Such protection was afforded by cross-coupling the input and outputs of the respective drivers by means of diodes in order to inhibit the operation of one of two output drivers in the event both drivers were energized simultaneously, and by adding combinations of resistance, capacitance and diodes to each of the respective driver inputs thereby inhibiting activation of a second driver circuit until the current was dissipated in the first driver circuit, and conversely. With this configuration, the ambiguous condition or latching condition will only occur with a component failure in the control circuitry.
Another approach of the prior art, requiring only one power supply, employs common-emitter drivers in a bridge-type circuit. Because of the bridge configuration, however, this circuit requires twice the number of active power devices as of the prior art system using a duplex supply. This circuit does eliminate the need for level shifting circuitry; however, in order to provide appropriate synchronism of the driver elements of the bridge cirbuit, additional logic level buffering must be provided in the control circuitry. As in the first prior art configuration control signals applied simultaneously or without appropriate delay between two input signals could result in catastrophic failure or logic ambiguity in the direction of energization of the electrical load. Therefore, as in the second prior art system, it was found necessary to provide additional protective circuitry to preclude latch-up occurrence.
While such prior art devices have provided satisfactory electrical performance, their relative complexity and large parts count has lead to efforts of simplification which have resulted in the present invention. A third prior art configuration using common-emitter drivers and low level transistor switches in a bridge configuration has also been employed. While permitting greatly reduced parts complexity, the circuit has also suffered from the aforementioned problems of latch-up in a potential race condition in which current through the driver continues even after the input signal has been removed. If the load is inductive and possesses sufficient energy storage capacity, it may result in catastrophic failure of the driver element.